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DS1621
 
NOTES:
1.   All voltages are referenced to ground.
 
2.   I/O pins of fast mode devices must not obstruct the SDA and SCL lines if V
DD
 is switched off. 
 
3.   I
CC
 specified with T
OUT
 pin open. 
 
4.   I
CC
 specified with V
CC
 at 5.0V and SDA, SCL = 5.0V, 0癈 to 70癈.
 
5.   After this period, the first clock pulse is generated.
 
6.   A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the
V
IH MIN
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
 
7.   The maximum t
HD:DAT
 
has only to be met if the device does not stretch the LOW period (t
LOW
) of the
SCL signal.
 
8.   A fast mode device can be used in a standard mode system, but the requirement t
SU:DAT
 >250ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line t
RMAX
+ t
SU:DAT
= 1000 + 250 = 1250ns before the SCL line is released.
 
9.   C
B
 total capacitance of one bus line in pF. 
 
10. Writing to the nonvolatile memory should only take place in the 0癈 to 70癈 temperature range.
 
 
TIMING DIAGRAM
 
 
 
 
 
16
axim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
axim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
axim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
haracteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
2
M xim In    r
Th  M xim l
n  M xim In    r
r   r
m rk    f M xim In    r
Pr
In .
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